作业帮VHDL wait for语句library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fpga_topp is port ( SPI_CS: OUT std_logic); end fpga_topp;architecture RTL of fpga_topp isBEGINPROCESS BEGIN loop1:loop SPI_CS
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VHDL wait for语句library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fpga_topp is port ( SPI_CS: OUT std_logic); end fpga_topp;architecture RTL of fpga_topp isBEGINPROCESS BEGIN loop1:loop SPI_CS
VHDL wait for语句
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fpga_topp is
port ( SPI_CS: OUT std_logic);
end fpga_topp;
architecture RTL of fpga_topp is
BEGIN
PROCESS
BEGIN
loop1:loop
SPI_CS
VHDL wait for语句library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fpga_topp is port ( SPI_CS: OUT std_logic); end fpga_topp;architecture RTL of fpga_topp isBEGINPROCESS BEGIN loop1:loop SPI_CS
你在用软件的思路设计硬件,是不会有结果的.
因为软件是顺序执行的,硬件是并行工作的.
你的设计实体要有输入信号,你想让输出信号SPI_CS每个周期(200ns)输出170ns低电平,30ns高电平,那就设计一个输入时钟信号clk,周期为10ns,设计计数器为0~19,每个clk周期加1,当计数器值为0~2时SPI_CS输出高电平,3~19时输出低电平就可以了.
你的进程需要敏感信号clk,在每个clk的有效边沿(例如上升沿)让计数器加1.
不需要LOOP语句,LOOP语句不是你想的那样执行循环体.一定记住你在描述硬件而不是执行软件指令.